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    • 专利摘要:
    The invention relates to a process for forming layers of group IIIA nitride, such as GaN, on substrates. The layers of group IIIA nitride can be deposited on semiconductor on insulator (SOI, for example, silicon on insulator) substrates with mesa patterns. The layers of group IIIA nitride can be deposited by heteroepitaxial deposition on semiconductor on insulator substrates (SOI, for example, silicon on insulator) with mesa patterns. Figure for abstract: None
    公开号:FR3087045A1
    申请号:FR1911190
    申请日:2019-10-09
    公开日:2020-04-10
    发明作者:Gang Wang；Michael R Seacrist
    申请人:GlobalWafers Co Ltd；
    IPC主号:
    专利说明:

    Description
    Title of the invention: Manufacture of group IIIA nitride layers on semiconductor structures on insulation [0001] RELATED REFERENCE TO APPLICATION [0002] The present application claims priority from the provisional patent application US n ° 62/095 282 filed December 22, 2014, the entire disclosure of which is incorporated herein by reference in its entirety.
    Technical Field [0003] The present invention relates generally to the field of manufacturing semiconductor wafers. More specifically, the present invention relates to a method of forming a group IIIA nitride layer on the device layer of a semiconductor on insulator structure (for example, silicon on insulator).
    BACKGROUND OF THE INVENTION The semiconductor wafers are generally prepared from a monocrystalline ingot (for example, silicon ingot) which is cut and ground to present one or more flats or notches with for orientation of the tranche in subsequent procedures. The ingot is then cut into individual slices. While we will be referring here to semiconductor wafers constructed from silicon, other materials can be used, such as silicon carbide, sapphire and aluminum nitride.
    [0006] The semiconductor wafers (for example, silicon wafers) can be used in the preparation of composite layer structures. A composite layer structure (for example, a semiconductor on insulator structure, and more specifically, a silicon on insulator (SOI) structure) generally includes a base wafer or layer, a device layer and a film insulator (i.e., dielectric) (usually an oxide layer) between the base layer and the device layer. Generally, the device layer is between 0.01 and 20 micrometers thick, for example, between 0.05 and 20 micrometers thick. In general, composite layer structures, such as silicon on insulator (SOI), silicon on sapphire (SOS) and silicon on quartz, are produced by placing two wafers in close contact and then performing heat treatment to strengthen the bond.
    After thermal annealing, the linked structure undergoes an additional treatment to remove a substantial part of the donor wafer to obtain the layer transfer. For example, wafer refining techniques, for example, by etching or grinding, can be used, often referred to as indentation SOI (i.e., BESOI), where a silicon wafer is bonded to a base wafer and then slowly removed by etching until only a thin layer of silicon remains on the base wafer. See, for example, U.S. Patent No. 5,189,500, the disclosure of which is incorporated herein by reference in its entirety. This process is time-consuming and expensive, wastes one of the substrates and generally does not have an appropriate thickness uniformity for layers thinner than a few microns.
    Another common method of obtaining layer transfer uses a hydrogen implant followed by a thermally induced layer separation. Particles (for example, hydrogen atoms or a combination of hydrogen and helium atoms) are implanted at a specified depth below the front surface of the donor wafer. The implanted particles form a cleavage plane in the donor wafer at the specified depth at which they were implanted. The surface of the donor slice is cleaned to remove organic compounds deposited on the slice during the implantation process.
    The front surface of the donor wafer is then bonded to a base wafer to form a bonded wafer through a hydrophilic bonding process. Before binding, the donor wafer and / or the base wafer are activated by exposing the surfaces of the wafers to plasma containing, for example, oxygen or nitrogen. Exposure to plasma changes the structure of surfaces in a process often called surface activation, which activates the hydrophilic surfaces of one or both of the donor wafer and the base wafer. The slices are then pressed together, and a bond is formed between them. This bond is relatively weak, and must be reinforced before being able to carry out a complementary treatment.
    In some methods, the hydrophilic bond between the donor wafer and the base wafer (i.e., a linked wafer) is strengthened by heating or annealing the pair of linked wafers. In some methods, wafer binding can occur at low temperatures, such as between about 300 ° C and 500 ° C. In some processes, wafer binding can occur at high temperatures, such as between about 800 ° C and 1100 ° C. The high temperatures cause covalent bonds to form between the adjoining surfaces of the donor wafer and the base wafer, thereby solidifying the bond between the donor wafer and the base wafer. In parallel with the heating or annealing of the bonded wafer, the particles implanted earlier in the donor wafer weaken the cleavage plane.
    Part of the donor wafer is then separated (i.e., cleaved) along the cleavage plane of the linked wafer to form the SOL wafer Cleavage can be performed only by placing the linked wafer in a frame where a force mechanical is applied perpendicular to the opposite sides of the linked wafer in order to separate part of the donor wafer from the linked wafer. According to certain methods, suction cups are used to apply mechanical force. The separation of the portion of the donor wafer is started by applying a mechanical wedge at the edge of the wafer linked to the level of the cleavage plane in order to start the propagation of a crack along the cleavage plane. The mechanical force applied by the suction cups then pulls the part of the donor wafer from the linked wafer, thus forming a SOL wafer. According to other methods, the linked pair can instead be subjected to a high temperature over a period of time to separate the part of the donor tranche from the linked tranche. Exposure to high temperature results in the creation and propagation of a crack along the cleavage plane, thereby separating part of the donor wafer. This process allows better uniformity of the transferred layer and allows recycling of the donor wafer, but usually requires the heating of the implanted pair and linked to temperatures approaching 500 ° C.
    The growth of the crystal in the mass of group IIIA nitrides, in particular GaN, constitutes a challenge and has not been successfully carried out in volume production. Typically, Group IIIA nitrides, such as GaN, are produced by heteroepitaxial deposition on wafer substrates made of sapphire, silicon carbide, and silicon. The deposition of group IIIA nitrides on semiconductor wafers constitutes a challenge due to the offset of the coefficient of thermal expansion (CTE - Coefficient of Thermal Expansion) between the GaN and the substrate, which leads to a strong bulging of the substrate. the wafer and cracks in the layer of group IIIA nitride deposited.
    Ordinarily, there are several technical approaches for responding to the residual voltage in the layers of group IIIA nitride, for example, of GaN, deposited heteroepitaxially on semiconductor substrates. In a solution, the layers of group IIIA nitride are deposited on thick semiconductor substrates. For example, silicon substrates having a thickness of at least about 1.0 millimeter, such as 1.5 millimeter, have been used to reduce wafer bulge caused by the heteroepitaxially deposited GaN layer. This approach does not change the tension, but attenuates the strain deformation of the substrate induced by the tension by increasing the rigidity of the substrate. Although the wafer bulge is reduced, the residual tension does not change and cracks in the GaN layer may remain present. Cracks are a harmful defect in the growth of thick GaN layers (> 5 µm) as used in high voltage power devices (> 800V). Layer cracking and edge bulging become more severe when the substrate diameter is extended to 200 mm or more.
    In another technique for reducing the defectiveness in the layer of group IIIA nitride deposited (for example, GaN), a buffer layer having a thickness of between approximately 2 micrometers and approximately 5 micrometers can be deposited on the wafer substrate before the formation of the group IIIA nitride layer (for example, GaN). The buffer layer may include aluminum nitride, aluminum nitride and gallium, or a multilayer comprising aluminum nitride and aluminum nitride and gallium. The residual tension in the AlN / AlGaN buffers tends to deform the substrate and thus create temperature non-uniformity across the substrate, which leads to non-uniformity in the thickness of the layer or its composition. . See Dadgar, Journal of Crystal Growth, 272 (2004) 72-75. Furthermore, the voltage in the GaN layer poses a problem in terms of device performance. See Zhang, J. Appl. Phys., 108, 073522 (2010).
    In another approach, the buffer structure is optimized to induce a compressive tension in the group IIIA nitride layer (for example, GaN) so that the tensile stress induced by the CTE shift can be partially compensated . An example of this technique is the use of a thin intermediate layer of low temperature AIN during the epitaxial growth of GaN. The GaN developed on an AIN or AlGaN layer with relaxed tension is subjected to a compressive stress. Since the dislocation in GaN has low mobility, the stress relaxation in the GaN layer is not complete. At the end of the epitaxy, a compressive tension is kept in the GaN layer to compensate for the tensile stress induced by the CTE shift. See, for example, Amano, J. Appl. Phys. 37, L1540 (1998), and Krost & Dadgar, Phys. Stat. Ground. (a) 200, No. 1, 26-35 (2003). Since the intermediate layer of AIN and the buffer layer of AlGaN only partially compensate for the tensile stress in GaN, the thickness of the crack-free GaN remains limited to a few micrometers.
    In yet another approach, group IIIA nitrides, such as GaN, are developed on patterned substrates. See, for example, U.S. Patent No. 8,507,737, which discloses the growth of GaN on patterned sapphire substrates. See also U.S. publication 2011/004568 which discloses grooved substrates. It has also been reported that GaN can grow on patterned Si (111) substrates. See Kawaguch, phys. stat. ground. (a) 176, 553 and Sawaki, Journal of Crystal Growth 311 (2009) 2867-2874. The object of this process is to release the tension at the edge of the GaN islets. However, stress relaxation is only effective in GaN layers having a lateral dimension of a few hundred micrometers.
    In addition, GaN has also been developed on compatible substrates. The growth of GaN on SOI substrates has improved crystal quality as reported by Cao, J. Appl. Phys., 83, 3829, 1998. However, there is no detailed study on the advantage of using SOI cover substrates in terms of cracking and stress relaxation. This approach can reduce the defectiveness of GaN, but does not necessarily increase the thickness of the crack-free GaN.
    Finally, the use of a rear side CTE layer to balance the bulge was disclosed in the publication U.S. ri 2012/0132921. Publication U.S. ri 2012/0132921 discloses a method for balancing the tensile stress in GaN using a layer of CTE on the back side of the substrate. The challenge of this process is that the reaction of the CTE film to the temperature change must follow that of the GaN.
    Summary of the Invention A method is provided for depositing layers of Group IIIA nitride on semiconductor on insulator (SOI) substrates. In some embodiments, the group IIIA nitride layers (eg, gallium nitride (GaN) layers) are formed by heteroepitaxial deposition on semiconductor on insulator substrates. Before the Group IIIA nitride layers are deposited, the semiconductor on insulator substrates are subjected to a process that produces a pattern of mesa islets in the device layer of the SOI substrate. In some embodiments, the mesa island pattern includes semi-floating, floating islands or combinations of both floating and semi-floating islands supported by support columns formed in the dielectric layer of SOI substrates. The group IIIA nitride layers can be formed on the mesa islands formed in the device layers. This process is designed to respond to the offset of the thermal expansion coefficients (CTE) between a group IIIA nitride, for example, GaN, and the substrate as well as to provide epitaxial templates of group IIIA nitride which are ready to be transferred to a dissimilar carrier substrate at low cost.
    In short, the present invention relates to a method of forming a multilayer structure. The method comprises: forming a pattern comprising a plurality of mesa islands on a semiconductor on insulator structure, the semiconductor on insulator structure comprising a base of monocrystalline semiconductor base, a dielectric layer in interfacial contact with the monocrystalline semiconductor base wafer, and a monocrystalline semiconductor device layer in interfacial contact with the dielectric layer, and further wherein the pattern comprising the plurality of mesa islands is formed in the monocrystalline semiconductor device layer; and forming a layer of Group IIIA nitride over the plurality of mesa islands.
    The present invention further relates to a multilayer structure comprising: a monocrystalline semiconductor base wafer comprising two generally parallel main surfaces, one of which is a front surface of the monocrystalline semiconductor base wafer and the other of which is a rear surface of the monocrystalline semiconductor base wafer, a circumferential rim joining the front and rear surfaces of the monocrystalline semiconductor base wafer, a volume region between the front and rear surfaces, and a central plane of the wafer monocrystalline semiconductor base between the front and rear surfaces of the wafer of monocrystalline semiconductor base; a dielectric layer in interfacial contact with a main surface of the monocrystalline semiconductor base wafer; a monocrystalline semiconductor device layer in interfacial contact with the dielectric layer, the monocrystalline semiconductor device layer comprising a pattern comprising a plurality of mesa islands; and a layer of group IIIA nitride on the mesa islets.
    The present invention further relates to a multilayer structure comprising: a carrier substrate; an interfacial bonding layer; and a layer of group IIIA nitride, the layer of group IIIA nitride having a thickness of between about 500 nanometers and about 1000 micrometers.
    Other objects and features of the present invention will be partly obvious and partly underlined below.
    Brief description of the drawings [fig.l] Figures IA to 1D illustrate an embodiment of the process of the present invention.
    [Fig-2] Figure 2A illustrates a pattern of semi-floating mesa islets on a substrate of
    SOI according to an embodiment of the present invention.
    FIG. 2B illustrates a pattern of floating mesa islets on an SOI substrate according to an embodiment of the present invention.
    [Fig.3] Figure 3A illustrates a multilayer structure according to an embodiment of the present invention. In one embodiment, the multilayer structure illustrated in FIG. 3A comprises a light-emitting diode (LED) device formed directly on a group IIIA nitride on mesa islets.
    FIG. 3B illustrates a multilayer structure according to an embodiment of the present invention. In one embodiment, the multilayer structure illustrated in FIG. 3B comprises a high electron mobility transistor (HEMT) supply device formed directly on a group IIIA nitride on mesa islets .
    [Fig.4] Figure 4 is an illustration of a lateral high electron mobility transistor (HEMT) supply device which can be constructed on a layer of group IIIA nitride on mesa islets.
    [Fig.5] Figures 5A to 5D illustrate an embodiment of the process of the present invention.
    DETAILED DESCRIPTION OF EMBODIMENT (S) OF THE INVENTION According to the present invention, a method is provided for forming a layer of group IIIA nitride, such as a layer comprising GaN, on a substrate . In certain embodiments, the layer of group IIIA nitride (for example, a GaN layer) is deposited on a semiconductor substrate on insulator with mesa patterns (SOI, for example, silicon on insulator). In certain embodiments, the group IIIA nitride layer can be deposited by heteroepitaxial deposition on semiconductor substrates on insulator with mesa patterns (SOI, for example, silicon on insulator). More particularly, a semiconductor on insulator structure is prepared to comprise a pattern comprising a plurality of mesa islands. The pattern comprising the plurality of mesa islands is formed in the monocrystalline semiconductor device layer (for example, a monocrystalline silicon device layer) of the SOI substrate. In the context of this disclosure, reference to a "device layer" is made to the layer of semiconductor material (typically, monocrystalline silicon) on an SOI substrate that results from a transfer process. classic layer used to form an SOI structure. In other words, an SOI structure includes a base wafer, a dielectric layer (usually a buried oxide layer, or BOX), and a device layer, and it is formed by a layer transfer. classic using a base slice and a donor slice. The device layer is derived from a monocrystalline semiconductor donor wafer. A "device layer" in the context of this disclosure does not necessarily refer to the semiconductor material in which a device can be formed. In contrast, in the context of the present disclosure, devices are generally formed in the group IIIA nitride layers formed by the process of the present invention. The group IIIA nitride layer can be formed on the mesa islands formed in the monocrystalline semiconductor device layer of an SOI substrate.
    In some embodiments, a buffer layer can be formed on the plurality of mesa islands formed in the layer of monocrystalline semiconductor device. The group IIIA nitride layer can be formed on the buffer layer formed on the mesa islets. In the context of the present invention, a mesa island formed in the monocrystalline semiconductor device layer (for example, a monocrystalline silicon device layer) includes a planar surface for deposition of a Group IIIA nitride. Essentially perpendicular to the deposition surface are side walls which define the contours of the mesa islets. The mesa islands are supported by the dielectric layer of the semiconductor on insulator structure.
    In some embodiments, the dielectric layer is modified by removing part of it, leaving support columns below the mesa islands. In some embodiments, therefore, the pattern of floating and semi-floating monocrystalline semiconductor mesa islands or combinations thereof is supported by the support columns derived from the dielectric layer. In the context of the present invention, a pattern of semi-floating islands comprises the interconnection or the formation of a bridge between the islands. See, for example, Figure 2A. The interconnection of the islands with a semiconductor material derived from the device layer helps to overcome by gravity induced layer collapse. In certain embodiments, for example, in FIG. 2B, the mesa islets are floating in that the islets do not have an interconnection bridge between the islets. In yet other embodiments, the pattern of the mesa islets can comprise both floating and semi-floating islets, namely, in certain segments of the wafer, the mesa islets can be connected by a semiconductor material, whereas in other segments of the section, the mesa islets are not connected. The method of the present invention is supposed to respond to the offset of the thermal expansion coefficients (CTE) between the GaN and the SOL substrate. In certain embodiments, the devices can be manufactured directly in the group IIIA nitride layer. formed on the motif of mesa islets. In some embodiments, the group IIIA nitride layer on the pattern comprising a plurality of mesa islands can be transferred to a dissimilar carrier substrate, and the group IIIA nitride layer can further undergo growth before manufacturing. devices in the group IIIA nitride layer. In some embodiments, the GaN templates developed on the SOI structure are easy to transfer to a dissimilar carrier substrate. The process allows the transfer of a layer of Group IIIA nitride to a dissimilar carrier substrate at low cost. In certain embodiments, after transfer of the group IIIA nitride layer to the dissimilar carrier substrate, it can be thickened. In some embodiments, the thickening technique includes epitaxial deposition. The devices can be manufactured in the thickened group IIIA nitride layer. In certain embodiments, the method of the present invention allows the manufacture of devices which can currently be manufactured only on a mass of GaN such as vertical GaN on a high voltage supply device for GaN, GaN on LEDs of GaN and laser diodes.
    1. Semiconductor on insulator substrate The substrates intended to be used in the present invention are semiconductor on insulator structures, for example, a silicon on insulator structure. See Figure IA. A semiconductor on insulator structure 10 is formed by bonding a semiconductor base wafer 12 and a semiconductor donor wafer. A dielectric layer 14 is located between the semiconductor base wafer 12 and the semiconductor device layer 16. During the manufacture of SOI, the intervening dielectric layer 14 can be formed on the front surface of the semi wafer base wafer. -conductive 12, or it can be formed on the semiconductor donor wafer. In some SOI manufacturing processes, the dielectric layers can be formed on the two wafers. The semiconductor device layer 16 in a semiconductor on insulator composite structure 10 is derived from the semiconductor donor wafer. The semiconductor device layer 16 can be transferred to the semiconductor base wafer 12 by wafer thinning techniques such as by etching a semiconductor donor substrate or by cleavage of a semiconductor donor substrate comprising a damage plan.
    In general, the monocrystalline semiconductor base wafer 12 and the monocrystalline semiconductor donor wafer (the device layer 16 is derived from the donor wafer in the manufacture of SOI) comprise two generally parallel main surfaces. One of the parallel surfaces is a front surface of the wafer, and the other parallel surface is a rear surface of the wafer. The edges include a circumferential rim joining the front and rear surfaces, and a central plane between the front and rear surfaces. The slices further include an imaginary central axis perpendicular to the central plane and a radial length which extends from the central axis to the circumferential edge. Furthermore, since the wafers, for example, silicon wafers, usually exhibit some variation in total thickness (TTV), deformation and bulge, the intermediate point between each point on the front surface and each point on the back surface may not lie precisely inside a plane. In practice, however, the TTV, the deformation and the bulge are usually so slight that in a close approximation, it can be said that the intermediate points lie inside an imaginary central plane which is approximately equidistant between the front and rear surfaces.
    If we look again at Figure IA, the semiconductor device layer 16 in a semiconductor on insulator composite structure 10 is derived from a monocrystalline semiconductor donor wafer. The semiconductor device layer 16 can be transferred to the semiconductor base wafer 12 by wafer thinning techniques such as by etching a semiconductor donor substrate and by cleavage of a semiconductor donor substrate including a damage plan. When performing conventional bonding and wafer thinning steps, the semiconductor on insulator composite structure (e.g., silicon on insulator) 10 includes the monocrystalline semiconductor base wafer 12, a dielectric layer 14 such as a buried oxide layer, and the monocrystalline semiconductor device layer 16. A finished SOI substrate is subjected to the formation of mesa patterns according to the process of the present invention, before deposition of the nitride layer. group IIIA. More specifically, the device layer 16 is subjected to a series of steps to thereby form a pattern of mesa islets in the semiconductor device layer. Refer to FIG. 1B on which there is a composite semiconductor on insulator structure 10 (for example, silicon on insulator) comprising a monocrystalline semiconductor base wafer 12, a dielectric layer 14 such as a layer of buried oxide, and a pattern of mesa islets 18, which are derived from the semiconductor device layer 16 of Figure IA. It is on this mesa block pattern 18 (Figures IB and IC) formed from the device layer 16 (Figure IA) that the group IIIA nitride layers are formed. In some embodiments, the mesa 18 island pattern may include semi-floating islands. Refer to Figure 2A, which is an example view from above of semi-floating mesa islets. In the context of the present invention, a pattern of semi-floating islands comprises the interconnection or the formation of bridges between islands. This is shown by the connecting islands of semiconductor material in Figure 2A, which is a top view of a pattern of interconnected mesa islands. The semiconductor bridging material, which is derived from the device layer 16 of Figure IA may be located substantially as shown in Figure 2A, but other bonding configurations are possible, such as substantial bonding at or at near the middle of the blocks, and in addition one block can be linked to an adjacent block, two adjacent blocks, three adjacent blocks, four adjacent blocks or even more blocks, depending on the shape of the blocks. In some embodiments, the mesa 18 island pattern may include floating islands. Refer to Figure 2B, which is a top view representation of floating mesa islets. As shown in FIG. 2B, the mesa islets are floating in that the islets do not have an interconnection bridge between the islets. In still other embodiments, the pattern of mesa islets may include both floating and semi-floating islets, i.e., in certain segments of the wafer, the mesa islets may be connected by a semiconductor material , while in other segments of the wafer, the mesa islets are not connected. Furthermore, the dielectric layer can also be etched to reveal support columns which support the mesa islands. Refer to FIG. 1C, which illustrates the composite semiconductor on insulator structure (for example, silicon on insulator) 10 comprising the monocrystalline semiconductor base wafer 12 and the mesa island pattern 18. The SOI structure 10 of Figure IC includes support structures 20 below each mesa island. The support structures 20 comprise a dielectric material (for example, silicon dioxide) since they are derived from the dielectric layer 14 as illustrated in Figures IA and IB.
    The semiconductor base wafer 12 and the device layer 16 may comprise a monocrystalline semiconductor material. In certain embodiments, the semiconductor material can be chosen from the group consisting of silicon, silicon carbide, sapphire and aluminum nitride. In some embodiments, the semiconductor may include silicon or sapphire. The base wafer 12 and the device layer 14 may comprise the same semiconductor material, or they may be different. In view of this, SOI 16 structures can include, for example, silicon on insulator, sapphire on insulator, aluminum nitride on insulator and other combinations. Semiconductor-on-insulator structures 16 typically have a nominal diameter of at least about 150 mm, at least about 200 mm, at least about 300 mm, or at least about 450 mm. The thicknesses can vary from about 250 micrometers to about 1500 micrometers, such as between about 300 micrometers and about 1000 micrometers, suitably in the range of about 500 micrometers to about 1000 micrometers.
    In particularly preferred embodiments, the semiconductor structures on insulator 10 are prepared from support wafers and donor wafers which are slices of monocrystalline silicon which have been cut from a monocrystalline ingot developed according to conventional Czochralski crystal growth methods or floating zone growth methods. These methods, as well as standard silicon cutting, lapping, etching, and polishing techniques are disclosed, for example, in L. Shimura, Semiconductor Silicon Crystal Technology, Academic Press, 1989, and Silicon Chemical Etching, (J. Grabmaier ed.) Springer-Verlag, NY, 1982 (incorporated here for reference). Preferably, the slices are polished and cleaned by standard methods known to those skilled in the art. See, for example, W.C. O’Mara et al., Handbook of Semiconductor Silicon Technology, Noyes Publications. If desired, the slices can be cleaned, for example, in a standard SCI / SC2 solution. In some embodiments, the monocrystalline silicon wafers of the present invention are monocrystalline silicon wafers which have been cut from a monocrystalline ingot developed according to conventional Czochralski (Cz) crystal growth methods, having ordinary a nominal diameter of at least about 150 mm, at least about 200 mm, at least about 300 mm, or at least about 450 mm. Preferably, both the monocrystalline silicon base wafer and the monocrystalline silicon donor wafer have mirror polished surface finishes that are free of surface defects, such as nicks, large particles, etc. The thickness of the wafer can vary from about 250 micrometers to about 1500 micrometers, such as from about 300 micrometers to about 1000 micrometers, usually in the range of about 500 micrometers to about 1000 micrometers. In certain specific embodiments, the thickness of the tench may be approximately 725 micrometers.
    In some embodiments, the monocrystalline semiconductor wafers, i.e., the base wafer and the donor wafer, include interstitial oxygen in concentrations which are generally obtained by the Czochralski growth process. In some embodiments, the semiconductor wafers include oxygen in a concentration between about 4 PPMA and about 18 PPMA. In some embodiments, the semiconductor wafers include oxygen in a concentration between about 10 PPMA and about 35 PPMA. In some embodiments, the basic monocrystalline silicon wafer includes oxygen in a concentration of not more than about 10 PPMA. Interstitial oxygen can be measured according to SEMI MF 1188-1105.
    The basic slice of monocrystalline silicon 12 can have any of a crystal orientation (100), (110) or (111). The crystal orientation of the base wafer 12 is often not critical since the base wafer 12 is often not part of the finished device. In some embodiments, the monocrystalline silicon donor wafer has a crystal orientation (111). Consequently and again with reference to FIG. 1A, the semiconductor on insulator structure 10 comprises a layer of monocrystalline device 14 having a crystal orientation (111). The orientation of the silicon crystal (111) is preferred in order to obtain high quality epitaxial growth of group IIIA nitride materials. Other crystal orientations, such as (100) and (110), are not as successful for epitaxial deposition of group IIIA nitrides. For example, the orientation of the silicon crystal (111) is preferred since it conforms to the hexagonal growth habit of GaN.
    In some embodiments the monocrystalline semiconductor base wafer 12, such as the monocrystalline silicon base wafer, and / or the semiconductor device layer 16, for example, a layer of monocrystalline silicon, has relatively high minimum volume resistivity. The high resistivity slices are generally cut from monocrystalline ingots developed by the Czochralski method or a floating zone method. The silicon wafers developed by Cz can be subjected to thermal annealing ranging from approximately 600 ° C to approximately 1000 ° C in order to annihilate the thermal donors caused by oxygen which are incorporated during the growth of the crystal. In some embodiments, the monocrystalline semiconductor base wafer has a minimum volume resistivity of at least 10 Ohm-cm, at least 100 Ohm-cm, at least about 500 Ohm-cm, at least at least about 1000 Ohm-cm, or at least about 3000 Ohm-cm, as between about 100 Ohm-cm and about 100,000 Ohm-cm, or between about 500 Ohm-cm and about 100 000 Ohm-cm, or between approximately 1000 Ohm-cm and approximately 100,000 Ohm-cm, or between approximately 500 Ohm-cm and approximately 10,000 Ohm-cm, or between approximately 750 Ohm-cm and about 10,000 Ohm-cm, from about 1000 Ohm-cm and about 10,000 Ohm-cm, from about 2000 Ohm-cm and about 10,000 Ohm-cm, from about 3000 Ohm-cm and about 10 000 Ohm-cm, or between about 3000 Ohm cm and about 5000 Ohm-cm. Methods for preparing high resistivity wafers are known in the art, and such high resistivity wafers can be obtained from commercial suppliers, such as SunEdison Semiconductor Ltd. (St. Peters, MO; formerly MEMO Electronic Materials, Inc.).
    To form the semiconductor on insulator structure 10, the monocrystalline semiconductor base wafer 12 is linked to a monocrystalline semiconductor donor wafer, for example, a monocrystalline semiconductor donor wafer, which is prepared according to methods conventional layer transfer. Namely, the monocrystalline semiconductor donor wafer can be subjected to standard processing steps including cleaning of oxidation, implantation and postimplantation. As a result, a monocrystalline semiconductor donor wafer of a material which is ordinarily used in the preparation of multilayer semiconductor structures, for example, a monocrystalline silicon donor wafer, which has been etched and polished and oxidized, is subjected to ion implantation to form a layer of damage in the donor substrate.
    The base wafer and the donor wafer are brought into close contact to thereby form a linked structure. Since the mechanical bond is relatively weak, the bonded structure is further annealed by conventional methods to solidify the bond between the donor wafer and the base wafer. After thermal annealing, the bond between the wafers is strong enough to start the layer transfer via cleavage of the linked structure at the level of the cleavage plane. Cleavage can occur according to techniques known in the art. If we look at Figure IA, the cleavage removes part of the semiconductor donor wafer, thus leaving a layer of semiconductor device 16, preferably, a layer of silicon device, in in terfacial contact with a dielectric layer 14 (i.e., a buried oxide layer or BOX), which is in contact with a monocrystalline semiconductor base wafer (for example, silicon) 12. The entire structure includes the semiconductor composite structure on insulator 10, which is the substrate for the process of the present invention.
    If we look again at FIG. 1A, between the support substrate 12 and the device layer 16, there is a dielectric layer 14. The materials of suitable dielectric layer 14 include silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide, barium oxide and a combination thereof. In some preferred embodiments, the dielectric layer 14 includes a buried oxide layer, i.e., a BOX. The thickness of the dielectric layer can be between about 10 nanometers and about 5000 nanometers, such as between about 10 nanometers and about 1000 nanometers, such as between about 50 nanometers and about 500 nanometers.
    The monocrystalline semiconductor device layer 16, for example, a monocrystalline silicon device layer, may have a thickness of between approximately 1 nanometer and approximately 500 nanometers, such as between approximately 5 nanometers and approximately 100 nanometers . Again, the SOI structure 10 preferably includes a device layer 16 having an Si (111) crystal orientation in order to achieve high quality epitaxial growth of group IIIA nitride materials.
    2. Formation of mesa islets in the device layer of a semiconductor substrate on insulator [0051] According to the method of the present invention, and with reference to FIG. 1B, a pattern comprising a plurality of mesa islets 18 is formed on a semiconductor on insulator structure 10. More specifically, the pattern comprising the plurality of mesa islets 18 is formed in the layer of monocrystalline semiconductor device 16. Compare FIG. IA and FIG. IB , which are illustrations illustrating the starting SOI substrate (FIG. 1A) and an SOI substrate comprising a pattern of mesa islets 18 (FIG. 1B), where the mesa islets are prepared in the semiconductor device layer of origin 16. The pattern comprising the plurality of mesa islands 18 preferably comprises shapes formed in the layer of semiconductor device 16 which are useful in the final structure which incorporates the layer of group III nitride AT. In some embodiments, the mesa islands 18 are formed by removing a portion of the monocrystalline semiconductor device layer 16. In some embodiments, the mesa islands 18 are formed by lithography. The lithography defines the patterns by photoresist. The elimination of the semiconductor material in the device layer 16, for example, of silicon between the islands, is carried out by selective etching of the semiconductor material, for example, of silicon by means of reactive ion etching (RIE) or a wet etching. In RIE, a Cl 2 gas selectively etches the semiconductor, for example, silicon. During wet etching, an aqueous KOH solution or an aqueous TMAH solution can be used. Once the device layer 16 is open, the photoresist is etched and the wafer is subjected to an HF solution to under-etch the BOX so that islands of floating and semi-floating mesa 18 (FIG. IC) are obtained. The shape of the islands is not essential, but rectangular or square shapes are preferred for the fabrication of devices on the GaN layers. See FIG. 2A illustrating a pattern of semi-floating mesa islands on an SOI substrate according to an embodiment of the present invention, and FIG. 2B illustrating a pattern of floating mesa islands on an SOI substrate according to an embodiment realization of the present invention.
    In some embodiments of the formation of mesa patterns, floating mesa islets, namely, mesa islets without interconnection bridges of semiconductor material, are not preferred because it is preferable to maximize the lateral dimension of the islets . In addition, the interconnection or bridging between the islands helps to overcome gravity induced layer subsidence. In some preferred embodiments, the portion of the monocrystalline semiconductor device layer 16 removed to form a pattern of mesa islands 18 in the monocrystalline semiconductor device layer leaves a pattern in which each mesa island has a quadrilateral shape, by example, square, rectangular, diamond, parallelogram, etc., when viewed from above. See, for example, Figures 2A and 2B for illustrations of an example of a suitable mesa island shape. In some embodiments, each side of the quadrilateral shape is between about 10 microns and about 10,000 microns in size. The dimensions of the mesa islands may depend on the chip size required for the desired end use. For example, the feeder chip sizes can range from about 1000 micrometers to about 10,000 micrometers. The chip sizes for LED devices can range from about 10 microns to about 1000 microns, such as between about 10 microns and about 500 microns. In addition, in some embodiments, the mesa islets may be separated by a space having a distance of between about 1 micrometer and about 100 micrometers.
    In some embodiments, the portion of the layer of monocrystalline semiconductor device 16 (FIG. 1A) removed to form a pattern of mesa islands 18 (FIGS. IB and IC) in the layer of monocrystalline semiconductor device leaves a pattern in which each mesa island has a rectangular shape, when viewed from above. See for example, Figures 2A and 2B, which are top views of an SOI structure in which part of the donor layer is removed to form a pattern comprising a plurality of rectangular mesa islets. In some embodiments, the portion of the monocrystalline semiconductor device layer 16 (Figure IA) removed to form a pattern of mesa islands 18 (Figures IB and IC) in the monocrystalline semiconductor device layer leaves a pattern in which each mesa island has a square shape, when viewed from above. In some embodiments, each side of the rectangular or square shape has a dimension between about 10 microns and about 10,000 microns. In addition, in some embodiments, the mesa islets are separated by a space having a distance between about 1 micrometer and about 100 micrometers.
    After elimination of part of the monocrystalline semiconductor device layer 16 to reveal a pattern of mesa islands 18 (for example, rectangular islands on the buried oxide layer) in the device layer as illustrated in FIG. 1B (and illustrated by way of example in FIGS. 2A and 2B), in certain embodiments of the invention, the SOI substrate 10 is etched to eliminate part of the dielectric layer 14 to thereby form a layer of structures of support 20 below the mesa islands 18. See FIG. 1C for an example of a non-limiting illustration of support structures 20 supporting a pattern of mesa islands 18. In certain embodiments, a dielectric layer 14, for example, of the silicon dioxide, is partially removed, such that a pattern of semi-floating or floating monocrystalline silicon mesa islands 18 or both is obtained. See figure IC. The dielectric layer 14, for example, the BOX, can be etched using hydrofluoric acid, either aqueous or in the vapor phase. In one embodiment, the dielectric layer 14 can be etched using an HF solution (0.5-10%) on a wet bench. In one embodiment, the dielectric layer 14 can be etched by means of HF steam in a closed chamber. In some embodiments, the dielectric layer 14 is etched such that the remaining support columns 20 (FIG. 1C) have essentially the same quadrilateral shape as the mesa islets 18 in the monocrystalline semiconductor donor layer, but with more small dimensions. Namely, the remaining dielectric layer material 20 (Figure IC), which supports the mesa islets 18, can essentially have a quadrilateral shape, for example, square, rectangular, diamond, parallelogram, etc., when viewed from above, and having smaller dimensions, thus leaving floating or semi-floating mesa islands 18 formed on the SOI substrate 10.
    In some embodiments, before deposition of the group IIIA nitride layer, the SOI substrate 10 comprising the pattern of mesa islets 18 can be cleaned. For example, in some embodiments, the SOI substrate 10 can be baked in a hydrogen atmosphere at a temperature between about 900 ° C and about 1100 ° C. These firing conditions may be suitable for cleaning the residual trace oxide on the layer of silicon device comprising the mesa islands.
    3. Deposition of buffer layer on mesa islands [0057] In certain embodiments, before deposition of the group IIIA nitride layer, a buffer layer may possibly be deposited on the pattern of mesa islands 18 formed in the monocrystalline semiconductor device layer of SOI substrate
    10. The buffer layer can comprise a layer of aluminum nitride formed on the pattern comprising the plurality of mesa islands 18. In certain embodiments, a layer of aluminum nitride can be deposited by chemical vapor deposition from organometallic compounds (MOCVD - MetalOrganic Chemical Vapor Phase Deposition) or epitaxy in vapor phase from organometallic compounds (MOVPE - MetalOrganic Vapor Phase Epitaxy), generally at a temperature between 800 and 1100 ° C. Molecular beam epitaxy is also an option for the deposition of AlN. Deposit instruments are commercially available from manufacturers such as Aixtron and Vecco. The aluminum nitride layer can be deposited at a thickness of between about 1 nanometer and about 500 nanometers, such as between about 10 nanometers and about 100 nanometers. The buffer layer may include a layer of aluminum and gallium nitride formed on the pattern comprising the plurality of mesa islands. In general, aluminum gallium nitride can be deposited by chemical vapor deposition from organometallic compounds (MOCVD) or vapor phase epitaxy from organometallic compounds (MOVPE), generally at temperatures between 800 and 1100 ° C. The layer of aluminum and gallium nitride can be deposited at a thickness of between approximately 1 nanometer and approximately 500 nanometers, such as between approximately 10 nanometers and approximately 100 nanometers. In certain embodiments, the buffer layer may comprise a layer of aluminum nitride and gallium formed on a layer of aluminum nitride before formation of the layer of group IIIA nitride on the pattern comprising the plurality of mesa islands .
    4. Deposition of group IIIA nitride layer on mesa islets [0059] If we look at FIG. 1D, the SOI structure 10 comprising the base of monocrystalline semiconductor base 12, the remaining part of the dielectric layer 20 comprising the support structures, and the pattern of semi-floating mesa 18 islands formed from the layer of monocrystalline semiconductor device supported by the remaining part of the dielectric layer 20 is then subjected to a deposition of a layer of group IIIA nitride 22. In the context of the present invention, group IIIA denotes the group of boron elements, including boron, aluminum, gallium and indium. As a result, Group IIIA nitrides include boron nitride, aluminum nitride, gallium nitride and indium nitride. In preferred embodiments, gallium nitride is deposited on the pattern of mesa islets. Gallium nitride can be deposited on a buffer layer, which has been previously deposited on the mesa islets. The group IIIA nitride layer can be deposited by chemical vapor deposition from organometallic compounds (MOCVD), vapor phase epitaxy from organometallic compounds (MOVPE), or molecular beam epitaxy (MBE). In certain preferred embodiments, the group IIIA nitride layer can be deposited by chemical vapor deposition from organometallic compounds (MOCVD). A suitable MOCVD reactor can be a Veeco TurboDisc or an Aixtron G5. Aluminum precursors suitable for MOCVD include trimethylaluminum and triethylaluminum. Gallium precursors suitable for MOCVD include trimethylgallium and triethylgallium. Indium precursors suitable for MOCVD include trimethylindium, triethylindium, di-isopropylmethylindium, and ethyldimethylindium. Nitrogen precursors suitable for MOCVD include ammonium, phenylhydrazine, dimethylhydrazine, tertiary butylamine and ammonia. Boron precursors include diborane, boron chloride, 1,3,5-tri (N-methyl) borazine. The molar ratio of the group V precursor (for example, ammonia) to the group IIIA precursor (for example, trimethylgallium) can be between 1 and 10,000, preferably between 100 and 1,000. A MOCVD reactor comprises a chamber comprising reactor walls, a lining, a susceptor, gas injection units and temperature control units. The parts of the reactor are made of materials that are resistant to precursor materials and not reactive to them. To prevent overheating, cooling water can flow through the channels inside the reactor walls. A substrate rests on a susceptor which is at a regulated temperature. The susceptor is made from a material resistant to the organometallic compounds used, such as SiC or graphite. Reactive gas is introduced through an inlet which controls the ratio of precursor reactants. Prior to the growth of GaN, an AIN seed layer can be deposited at a thickness of between about 1 nanometer and about 200 nanometers, or between about 5 nanometers and about 100 nanometers, or between about 50 nanometers and about 100 nanometers. The growth temperature can be between about 600 ° C and about 1200 ° C, such as between about 800 ° C and about 1200 ° C, preferably between about 1000 ° C and about 1150 ° C. Group IIIA nitride can be formed under reduced pressure, such as between about 10 Torr and about 760 Torr (about 101 kPa), preferably, between about 10 Torr (about 1.33 kPa) and about 80 Torr (about 10 , 67 kPa). During the growth of GaN, the diffusion of precursors from the gas phase towards the cavities between two adjacent mesa islets is delayed, which also eliminates the deposition of nitride materials. The layer of group IIIA nitride can be deposited at a thickness of between approximately 500 nanometers and approximately 200 micrometers, such as between approximately 500 nanometers and approximately 100 micrometers, or between approximately 1 micrometer and approximately 50 micrometers, or between approximately 2 micrometers and about 10 micrometers. The stress in the nitride layers is released both by unsuitable dislocations and the elastic deformation of the semi-floating Si layer.
    The layer of group IIIA nitride deposited according to the process of the present invention may have a density of through dislocations between approximately 10 6 / cm 2 and approximately 10 9 / cm 2 , such as between approximately lOVcm 2 and approximately 10 8 / cm 2 . In certain embodiments of the present invention, the group IIIA nitride layer may be deposited to a thickness such that the density of through dislocations is less than about 10 6 / cm 2 , such that between about lOVcm 2 and about 10 6 / cm 2 , or between about 10 3 / cm 2 and about lOVcm 2 . The process of the present invention allows the growth of thick GaN layers without cracks. It is known that the density of through dislocations (TDD - Threading Dislocation Density) (Kapper, JCG, 300, 70 (2007) depends on the thickness of the layer of group IIIA nitride. According to the process of the present invention, layers thick GaNs can be developed, leading to reduced TDDs, however, the thickness of the epitaxial GaN layer from conventional GaN growth on cover substrates is limited by layer cracking due to the coefficient shift thermal expansion (CTE Coefficient of Thermal Expansion) between the GaN and the substrate, which is generally less than 5 μm in conjunction with a through dislocation density of approximately 10 8 / cm 2. The process of the present invention makes it possible to overcome the CTE stresses due to the growth of GaN on mesa islets. Consequently, the thickness of the GaN layer can be extended to 10 µm and more, even reaching 100 micrometers. very or more, which leads to a significantly reduced density of through dislocations.
    Another defect technique can be applied to reduce through dislocations, such as the formation of SiNx nanopatterns in situ. See Kapper, JCG, 300, 70 (2007) and US Patent Ri 7,708,832 B2. The formation of nanopatterns involves the use of dielectrics (such as Si 3 N 4 ) to block or terminate through dislocations on the surface before growth of the GaN layer. As the dielectric is thin (~ lnm), it has orifices which allow access to the underlying epitaxial GaN layer in the subsequent epitaxial growth. The lateral epitaxial growth above the dielectric mask promotes the formation of a continuous layer. See Kapper. The dielectric mask can be formed in the reaction reactor.
    MOCVD (in-situ) or by other deposition techniques, such as CVD, ALD, etc. The dielectric mask layer can be Si 3 N 4 , SiO 2 or another oxide.
    5. Device structures manufactured in the group IIIA nitride layer In certain embodiments and with reference to FIG. 3A, once the deposition of the group IIIA nitride layer 108 is finished on the pattern of mesa islets 106 formed in the monocrystalline semiconductor device layer (16 in Figure IA), multiple quantum wells and a contact layer of P-GaN 110 can be developed directly to complete an LED device structure. The growth of quantum wells is explained in the literature. See for example, Zhang, phys. stat. ground. (a) 188, No. 1, 151-154 (2001)]. After formation of quantum wells in the group IIIA nitride layer, the structure 100 comprises the monocrystalline semiconductor base wafer 102, a layer of support structures 104 derived from the dielectric layer (for example, buried oxide layer, and 14 in FIG. 1A), a layer comprising the pattern of mesa islands 106 (derived from the device layer 16 in FIG. 1A), the layer of nitride of group IIIA 108 formed on the layer comprising the pattern of mesa islands 106 , and the multiple quantum wells and the P-GaN 110 contact layer formed in the layer of group IIIA nitride 108. In certain embodiments, the mesa islets 106 comprising group IIIA nitride 108 and the quantum wells 110 are transferred to another substrate, such as glass to complete the fabrication and packaging of the LED device.
    In certain embodiments and with reference to FIG. 3B, once the deposition of the group IIIA nitride layer 108 on the pattern of mesa islets 106 formed in the monocrystalline semiconductor donor layer has ended, a device lateral of high electron mobility transistor (HEMT) 120, 122 can be developed directly on the nitride layer of group IIIA 108. The HEMT device can be used as a power supply device or as a radiofrequency device. The chip can then be detached and mounted directly in a housing. The thin structure (thin silicon with heteroepitaxial layers) would help minimize losses of thermal conductivity. A lateral high electron mobility transistor (HEMT) device 140 which can be fabricated on a group IIIA nitride, for example, GaN, is illustrated in Figure 4. See also, for example, Joshin, Proceedings of Asia -Pacific Microwave Conference, 2006. In the lateral HEMT device 140 illustrated in FIG. 4, the electrons move horizontally from the source 142 towards the drain 144 along the two-dimensional electron gas 148 (2DEG) formed at the interface between the AlGaN layer 146 and the GaN layer 150. The voltage of the gate 152 modulates the 2DEG 148 to open and close the current path. A high electric field is accumulated between the drain 144 and the grid 152 and a breaking voltage is usually limited by this electric field. The electron density of the
    2DEG 148 determines the resistance in the on state (R on ) and the drive current. As the electron density of 2DEG 148 (5-10xl0 12 / cm 2 ) is induced by polarization effect, the residual voltage of the CTE shift can modify the performance of the device as well as the reliability of the device. See Jocob Leach and Hadis Morkoc, Proceedings of the IEEE, 1127, V98, No. 7, July 2010. The present invention allows the reduction of the residual voltage resulting from the shift of the CTE and provides a more stable device performance.
    Another advantage of the present invention is that it provides the option of transferring the layer of high-quality group IIIA nitride (for example, a layer of GaN deposited by epitaxial deposition) to another carrier substrate which is developed to cover the application of the device. For example, an insulating or semi-insulating or high resistivity carrier substrate, such as a polycrystalline sapphire or AIN, is used for HEMT radiofrequency (RF) devices constructed in GaN layers to minimize RF loss and signal distortion . HEMT RF devices include structures similar to HEMT power devices, but operate at lower voltages. The structure of the HEMT RF is a lateral structure like that of the high voltage power supply device (600V). Since the voltage requirement is much lower (<100V), the GaN layer may not be as thick as for a supply device, but on the other hand, the structure and sequence of the layer are usually identical . These devices are designed on semi-insulating substrates to avoid the coupling of substrate in high frequency signal, in high resistivity silicon (> 1000ohm-cm) of the GaN / Si case (11) of Nitronex. A highly conductive carrier substrate, such as diamond or diamond-coated Si, can be used for HEMT power devices to facilitate heat dissipation.
    In some embodiments, the structure as illustrated in Figure 1D is suitable for use as a starting point in the manufacture of high voltage power supply devices. In the manufacture of high-voltage power devices, the mesa islands comprising the group IIIA nitride material (e.g., GaN) can be transferred to a carrier substrate for further growth of the group IIIA nitride material and subsequent manufacture of the device. In certain embodiments, the carrier substrate has properties of high thermal conductivity and low electrical conductivity. In some embodiments, the carrier substrate may include a high resistivity monocrystalline semiconductor substrate, such as a high resistivity monocrystalline silicon substrate, a polycrystalline silicon substrate, an aluminum nitride substrate, a sapphire, a polycrystalline aluminum nitride substrate, a diamond substrate, a diamond-coated silicon wafer, and the like. If we now look at Figures 5A to 5D, a multilayer structure 200 is provided, comprising a base of monocrystalline semiconductor base 202, a layer of support structures 204 derived from the dielectric layer (for example, a buried oxide layer , and 14 in FIG. 1A), a layer comprising the pattern of mesa islands 206 (derived from the device layer 16 in FIG. IA), and the layer of group IIIA nitride 208 formed on the layer comprising the pattern d 'mesa islets 206.
    In some embodiments, a thin interfacial bonding layer 210 is deposited on the group IIIA nitride layer 208. In some embodiments, the thin interfacial bonding layer 210 comprises between about 1 nanometer and about 5 nanometers aluminum oxide (A1 2 O 3 ). The interfacial bonding layer 210 can be deposited by atomic layer deposition or molecular beam epitaxy.
    After depositing the interfacial bonding layer 210, the layer can be activated for bonding by plasma activation of oxygen or nitrogen. In some embodiments, the oxygen plasma surface activation tool is a commercially available tool, such as those available in the EV group, such as the EVG® low temperature plasma activation system. 810LT. The optionally cleaned monocrystalline semiconductor donor wafer is loaded into the chamber. The chamber is evacuated and refilled with O 2 at a pressure below atmospheric pressure to thereby create the plasma. The multilayer structure of SOI 200 is exposed to this plasma for the desired time, which can range from approximately 1 second to approximately 120 seconds. The surface oxidation by oxygen plasma is carried out in order to make the front surface of the interfacial bonding layer 210 hydrophilic and capable of forming the bond to a monocrystalline semiconductor base substrate prepared according to the method described above.
    If we now look at FIG. 5B, the multilayer structure 200 comprising a base of monocrystalline semiconductor base 202, a layer of support structure 204 derived from the dielectric layer (for example, buried oxide layer, 14 on FIG. 1 A), a layer comprising the pattern of mesa islands 206 (derived from the device layer 16 in FIG. IA), and the layer of group IIIA nitride 208 formed on the layer comprising the pattern of mesa islands 206, and the activated interfacial bonding layer 210 is then bonded to a base or carrier substrate 220. The base or carrier substrate 220 can be any substrate that is suitable for a specific application. For HEMT power devices, substrates with good thermal conductivity, such as diamond substrates, are suitable. For vertical feeding devices, metallic substrates, such as copper substrates, are suitable. For LED devices, a transparent substrate, such as sapphire or glass, is suitable. For HEMT RF devices, semi-insulating or insulating substrates are preferred, such as sapphire, high resistivity Si, Γ AIN, etc. The bond between the multilayer structure 200 and the carrier substrate 220 does not need to be strong. In some embodiments, the base substrate 220 provides only support for the GaN mesa island. In some embodiments, there is no consecutive link removal process, such as cleavage. In some embodiments, the interface layer is optional, provided that a plasma activation assisted binding process is used.
    According to the process of the present invention, the dielectric layer 204 is etched to eliminate the dielectric layer and the basic substrate of monocrystalline silicon 202. In certain embodiments, the dielectric layer is etched by immersing the bonded structure in a etching solution comprising 1-10% HF. Once the remaining dielectric layer has been etched, the mesa island pattern 206 and the group IIIA nitride layer 208 are released from the monocrystalline silicon base substrate 202 and are transferred to the carrier substrate 220. At the level of the interface of the group IIIA nitride layer 208 and the carrier substrate 220, the interfacial bonding layer 210 is partially etched and weakens the bonding resistance, which adapts to any potential thermal stress in the thickening process of consecutive group IIIA nitride.
    According to the process of the present invention, the mesa islets formed in the monocrystalline semiconductor donor layer 206 are then removed to thereby prepare the structure 230 shown in FIG. 5C comprising a carrier substrate 220, the interfacial bonding layer 210 and the group IIIA nitride layer 208. This process of transferring layer to a different substrate provides versatile options for a different device application. On the GaN mesa islands as transferred, LEDs, a HEMT power device and a HEMT radio frequency device can be constructed. The mesa islets formed in the monocrystalline semiconductor donor layer 206 can be removed by etching either by wet chemistry, such as HNO 3 / HF and TMAH solution or by plasma etching. In certain embodiments in which buffer layers comprising ΓΑ1Ν and / or AlGaN are present, plasma etching is preferred. Plasma etching is also suitable for removing defective layers of group IIIA nitride. After removal of the defective top layers, a layer of high quality group IIIA nitride 208 (e.g., GaN) having through dislocations between about 10 6 / cm 2 and about 10 '/ cm 2 , such as between about 10 7 / cm 2 and approximately 10 8 / cm 2 , is left on the carrier substrate 220.
    In certain embodiments and with reference to FIG. 5D, the layer of high-quality group IIIA nitride 208 (for example, of GaN) can be thickened. In certain embodiments, the high-quality group IIIA nitride layer 208 (for example, GaN) can be thickened by epitaxial deposition, for example, by vapor phase epitaxy from organometallic compounds (MOVPE) or epitaxy by hydride vapor phase (HVPE). Commercially available HVPE reactors include the Aura HVPE system from Agnitron Technology, Inc. Ga precursors can be synthesized GaN powder or Ga liquid. HCl vapor gas is used to convert GaN or Ga liquid as a precursor of GaCl. NH 3 is used as a nitrogen precursor. Ar is used as the carrier gas. The growth of GaN occurs at a temperature between about 1000 ° C and about 1200 ° C, usually from about 1000 ° C to about 1100 ° C. The growth rate can be as high as 100 micrometers per hour. In some embodiments, the group IIIA nitride layer can be thickened to a thickness of between about 2 micrometers and about 50 micrometers, preferably between about 5 micrometers and about 10 micrometers. In some embodiments, the group IIIA nitride layer may be thickened to a thickness between about 2 micrometers and about 2000 micrometers, such as between about 2 micrometers and about 1000 micrometers, or between about 100 micrometers and about 300 micrometers .
    In certain embodiments, the thickened group IIIA nitride layer, for example, the GaN layer, can be doped during the growth process. In certain embodiments, the group IIIA nitride layer can be doped with an N-type dopant, such as silicon Si, germanium Ge, sulfur S, selenium Se and tin Sn. Suitable precursors which can be incorporated into the gas formula during the growth of the layer in order to boost the layer with an N-type dopant can include SiH 4 , GeH 4 , H 2 S, H 2 Se, and (C 2 H 5 ) Sn. In certain embodiments, the group IIIA nitride layer can be doped with a P-type dopant, such as Mg or Zn. Suitable precursors which can be incorporated into the gas formulation during the growth of the layer in order to boost the layer with an N-type dopant may include bis (cyclopentadienyl) magnesium, diethyl zinc and dimethyl zinc. In certain embodiments, the thickened layer of group IIIA nitride, for example, the GaN layer, can be doped with silicon. In some embodiments, SiH 4 gas may be added to the gas formula during the thickening process of the Group IIIA nitride layer in order to dop the layer with Si. In some embodiments, gas of SiH 4 can be added during the thickening of the GaN layer in order to boost the GaN layer with Si. The inclusion of SiH 4 during the thickening of the group IIIA nitride layer can lead to doping layer with Si to thereby prepare an n-type layer of group IIIA nitride.
    The inclusion of SiH 4 during the thickening of the GaN layer can lead to doping of the layer with Si to thus prepare the N-type GaN layer. The dopant concentration can range from approximately I × 10 15 doping atoms / cm 3 to about 5 × 10 20 doping atoms / cm 3 . In certain embodiments for preparing layers of group IIIA N- nitride, the concentration of dopant Si can range from approximately I × 10 15 doping atoms / cm 3 to approximately 3 × 10 17 doping atoms / cm 3 , such as from approximately IxlO 16 doping atoms / cm 3 to about 3xl0 16 doping atoms / cm 3 . In certain embodiments for preparing nitride layers of group ΠΙΑ N +, the concentration of the doping Si can range from approximately I × 10 18 doping atoms / cm 3 to approximately 5 × 10 20 doping atoms / cm 3 , such as from approximately I × 10 19 doping atoms / cm 3 to about 3xl0 20 doping atoms / cm 3 . In certain embodiments, for example, embodiments in which the group IIIA nitride layers are intended for vertical high-voltage supply devices of gallium nitride on gallium nitride, the dopant level can be modified during growth of the thickened group IIIA nitride layer. The variation in the dopant level allows the growth of a group IIIA nitride layer having multiple layers having different dopant concentrations. In certain embodiments, the group IIIA nitride layer may first of all be doped with an N- dopant, such as Si, at a dopant level of approximately I × 10 15 doping atoms / cm 3 to approximately 3 × 10 17 atoms dopants / cm 3 , such as from approximately IxlO 16 doping atoms / cm 3 to approximately 3xl0 16 doping atoms / cm 3 , which is followed by the formation of an N + layer by increasing the level of dopant between approximately IxlO 18 doping atoms / cm 3 at approximately 5 × 10 20 doping atoms / cm 3 , such as from approximately I × 10 19 doping atoms / cm 3 to approximately 3 × 10 20 doping atoms / cm 3 .
    Multilayer structures 230 comprising the carrier substrate 220, the interfacial bonding layer 210, and the thickened layer of group IIIA nitride 208, as illustrated in FIG. 5D, are suitable for the manufacture of HEMT supply devices with a target application of 800-1000V. The structures are also suitable for HEMT RF devices, LEDs, laser diodes, and vertical high-voltage power supplies of gallium nitride on gallium nitride, among other uses.
    In certain embodiments, the multilayer structures 230 comprising a carrier substrate 220, the interfacial bonding layer 210 and the thickened layer of group IIIA nitride 208, as illustrated in FIG. 5D, can also be subjected to additional growth by epitaxy, for example, hydride vapor phase epitaxy (HVPE), to achieve a target thickness of at least about 50 micrometers, such as between about 50 micrometers and about 2000 micrometers, or between about 50 micrometers and about 1000 micrometers, such as between about 100 micrometers and about 500 micrometers. Thickened layers of group nitride
    ΠΙΑ can be obtained with a reduced through dislocation density. In certain embodiments, the layers of group IIIA nitride having a thickness of between approximately 50 micrometers and approximately 2000 micrometers, such that between approximately 100 micrometers and approximately 1000 micrometers can have a through dislocation of less than 10 6 / cm 2 , such as between about lOVcm 2 and about 10 6 / cm 2 , or between about lOVcm 2 and about 10 5 / cm 2 , which is compared to massive GaN materials. Such structures 230 are suitable for use in the manufacture of vertical power devices (for example, HEMT power devices) and laser diodes as well as high brightness LEDs. See, for example, Uesugi, CS MANTECH Conference, Florida, 2009. A vertical power device is suitable for managing a high power, such as 20kW and higher. The structures 230 illustrated in FIG. 5D are also suitable for vertical high voltage supply devices of gallium nitride on gallium nitride. See, for example, Kizilyalli et al., Vertical Devices in Bulk GaN Drive Diode Performance to Near-Theoretical Limits, H0W2P0WER TODAY, March 2013. The advantage of the vertical power device over the lateral HEMT device is: a smaller size , a higher breaking voltage and a lower parasitic inductance. However, given the flow of current through the entire GaN layer, the quality requirements for GaN, such as for through dislocations and impurities, are more stringent. So far, a vertical feeder has been fabricated on massive, small GaN substrates that are expensive. In the present disclosure, as the growth of GaN takes place on floating or semi-floating mesa islets, a viable approach to the growth of thick GaN materials is obtained which have physical and electrical properties comparable to those of massive GaN substrates. at lower cost. The disclosed method uses a conventional growth method, MOCVD or MOVPE and is adaptable to manufacture on large substrates.
    The present invention therefore provides thick layers of high quality Group IIIA nitride, suitable GaN layers, without cracks. The Group IIIA nitride layers can be deposited at thicknesses of at least 500 nanometers, and can be developed up to 1000 micrometers thick. The method of the present invention minimizes the residual voltage in the GaN layer, thereby reducing the impact of the voltage on the performance of the device. The technique is suitably adapted to a large slice size up to 200 mm and beyond. The method of the present invention provides layer transfer options, eliminates potential damage to the RF power device from the conductive layer between the AIN seed layer and the Si substrate due to autodoping Al in Si. The method of the present invention allows the integration of optoelectronic devices with CMOS devices on Si substrates. The method of the present invention improves the quality of GaN to stimulate the performance of LED devices, RF, feeding.
    Having proceeded to a detailed description of the invention, it appears obvious that modifications and variations can be made without departing from the scope of the invention defined in the appended claims.
    Since various changes can be made to the above compositions and processes without departing from the scope of the invention, it is understood that all the material contained in the above description will be interpreted as illustrative and not as limiting.
    During the introduction of the elements of the present invention or of / a preferred embodiment (s) thereof, the articles "a", "an", "the", " the ”and“ the said ”are meant to mean that there are one or more of the elements. The terms "comprising", "including" and "having" are intended to be inclusive and to mean that there may be elements in addition to the elements listed
    权利要求:
    Claims (1)
    [1" id="c-fr-0001]
    Claims [Claim 1] Multilayer structure comprising:a carrier substrate;an interfacial bonding layer; anda layer of group IIIA nitride, the layer of group IIIA nitride having a thickness of between approximately 500 nanometers and approximately 2000 micrometers. [Claim 2] The multilayer structure of claim 1, wherein the layer of group IIIA nitride is between about 500 nanometers and about 100 micrometers thick. [Claim 3] The multilayer structure of claim 2, wherein the group IIIA nitride layer is between about 2 microns and about 10 microns thick. [Claim 4] The multilayer structure according to claim 2, wherein the group IIIA nitride layer comprises through dislocations at a through dislocation density between about 10 6 / cm 2 and about 10 9 / cm 2 . [Claim 5] A multilayer structure according to claim 2, wherein the group IIIA nitride layer comprises through dislocations at a through dislocation density between about lOVcm 2 and about 10 8 / cm 2 . [Claim 6] The multilayer structure of claim 1, wherein the layer of group IIIA nitride is between about 100 microns and about 1000 microns thick. [Claim 7] The multilayer structure of claim 6, wherein the layer of group IIIA nitride is between about 100 microns and about 300 microns thick. [Claim 8] The multilayer structure of claim 6, wherein the group IIIA nitride layer comprises through dislocations at a through dislocation density of less than about 10 6 / cm 2 . [Claim 9] The multilayer structure according to claim 6, wherein the group IIIA nitride layer comprises through dislocations at a through dislocation density between about lOVcm 2 and about 10 5 / cm 2 . [Claim 10] The multilayer structure according to claim 1, wherein the carrier substrate is selected from the group consisting of sapphire and polycrystalline aluminum nitride.
    [Claim 11] The multilayer structure of claim 1, wherein the carrier substrate is selected from the group consisting of diamond and diamond-coated silicon. [Claim 12] The multilayer structure according to claim 1, further comprising quantum wells formed in the group IIIA nitride layer and a P-GaN contact layer. [Claim 13] The multilayer structure of claim 1, further comprising the components of a lateral HEMT feeder. [Claim 14] The multilayer structure of claim 1, further comprising the components of a lateral HEMT radio frequency device. [Claim 15] The multilayer structure of claim 1, further comprising the components of a light emitting diode. [Claim 16] The multilayer structure of claim 1, further comprising the components of a laser diode. [Claim 17] The multilayer structure of claim 1, further comprising the components of a high voltage vertical gallium nitride on gallium nitride supply device.
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    法律状态:
    2019-10-22| PLFP| Fee payment|Year of fee payment: 5 |
    2020-12-27| PLFP| Fee payment|Year of fee payment: 6 |
    2021-10-08| PLSC| Publication of the preliminary search report|Effective date: 20211008 |
    2021-12-27| PLFP| Fee payment|Year of fee payment: 7 |
    优先权:
    申请号 | 申请日 | 专利标题
    US201462095282P| true| 2014-12-22|2014-12-22|
    US62/095,282|2014-12-22|
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